1. Field of the Invention
The present invention relates to a semiconductor device and more particularly, a semiconductor device having an address transition detecting circuit. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for securing a pulse width enough to allow a data transition when a single address signal is received.
2. Discussion of the Related Art
A background art ATD (Address Transition Detector) in a semiconductor memory device may malfunction due to unwanted ATD pulse generated by a noise from an internal circuit during operation, which causes a wrong detection of "high or low" value. Particularly, when a single ATD signal is applied, an accurate transmission of the address signal is difficult because an adequate pulse width can not be secured at the time of equalizing an I/O signal and transmission of an address transition signal. For example, as shown in FIG. 1A, when an I/O equalizing point is in general at a voltage of 2 V, the voltage applied and reached to the I/O equalizing point delivers "high" or "low" values to the next address in response to an address transition signal received. However, as shown in FIG. 1B, the applied voltage is higher than the 2 V of the I/O equalizing point, an exact reception and transmission of the next address transition signal is not possible. In addition, when a single ATD signal is received, an exact reading of the previous address signal at the I/O equalizing point is not possible due to a short pulse width. Thus, there has been a need to develop an address transition detecting circuit which can solve a drawback of the background art ATD circuit.
The background art ATD circuit will be explained with reference to the attached drawing. FIG. 2 illustrates a circuit diagram showing operation of the background art address detecting circuit having a multiple address transition detecting circuit adapted to receive a 2n number of address transition signals AT.sub.1 .about.AT.sub.2n. Specifically, an n number of NOR gates NOR1, NOR2, NOR3.about.NORn each receives two of the address transition signals AT.sub.1 .about.AT.sub.2n in an order and is subject to a logical summation and inversion. A NAND gate receives signals from the n number of NOR gates and is subject to a logical production and inversion to provide a final address transition signal.
The operation of the aforementioned background art ATD circuit will be explained with reference to FIG. 3 illustrating waveforms for showing operation of the background art ATD circuit.
Referring to FIG. 3 when multiple high address signals are received from the first high address signal to the last high address signal in succession, a high signal can be provided through the ATD terminal. That is, when a high signal is received, the address transition detecting circuit can provide the high signal. When a multiple address transition signal is required, a pulse width wide enough to detect an address transition signal at the data I/O equalizing point can be secured. On the contrary, when a single address transition signal is received, a pulse width wide enough to transmit an address transition signal at the I/O equalizing point can not be secured because a pulse width only as much as the received single address transition signal can be secured.
As a result, the background art ATD circuit has the following problems.
An enough pulse width can not be secured at an I/O equalizing point when a single address transition signal is received: Particularly, when a high source voltage is received, an address signal is not accurately transmitted because no proper data I/O equalization can be achieved in the background art ATD circuit.